1. Field of Invention
This invention relates to recovery of symbol timing of a signal received in a digital communication system. The invention is more particularly related to the detection of symbol edges for use in symbol timing recovery of low resolution digital signals encoded in an analog received signal.
2. Discussion of Background
In general digital communication systems, a transmitting apparatus modulates a digital signal (1) by any known modulation techniques (Quadrature Amplitude Modulation (QAM), or Quadrature Phase Shift Keying (QPSK), for example). The modulation technique converts the digital signal into an analog signal for transmission. A receiver of the analog modulated signal demodulates the signal and converts it into a digital signal, restoring it to the original form (digital signal (1)).
Many modulation and demodulation techniques are know that are capable of accurately restoring the received signals into original digital signals (also referred to as symbol values) when the received signals are sampled at the same interval of time (frequency) and symbol starting point (phase) as those of the symbols transmitted from the transmitter. Without proper frequency and phase alignment in the receiver (Rx), increased computations are required to maintain accuracy of the digital signal restoration, or additional errors are encountered (increasing a bit error rate (BER) of the communications system in general, and the receiver in particular). Therefore, one of the important processes that occur in the receiver of the digital communication system is to accurately restore a symbol timing (frequency and phase) representing a point in time that the received signal should be sampled.
In some systems, a specific carrier corresponding to a sampling frequency is transmitted, providing frequency and phase for the sampling. However, many modern systems do not provide a carrier, and it is therefore important to accurately recover a symbol timing using only the received signal. With the proliferation of digital communication systems, there has been an increased need for improved and distinctive symbol timing recover (STR) processes within receivers of digital communications. A conventional apparatus for recovering a symbol timing is shown in FIG. 1.
In FIG. 1, a received signal is input to an analog-to-digital (A/D) converter 100. The A/D converter 100 samples the input signal at a frequency supplied from a voltage controlled oscillator (VCO) 110 and converts the analog signal into a digital signal. The digitized signal is output via a matching filter 120, and simultaneously input to a timing error detector 130. The timing error detector 130 detects a symbol timing error from the input signal and outputs a detected error value, to a loop filter 140. The loop filter 140 filters the input signal to remove various noises. The VCO 110 oscillates at a frequency according to the output of the loop filter 140 and supplies the oscillated frequency signal to the A/D converter 100.
However, in conventional systems, receiver (Rx) and transmitter (Tx) inaccuracies, operating conditions, and other reasons can cause symbol timing drift that results in the number of symbols transmitted from the transmitter differs or has significantly different timing from that of the restored signals. For example, one reason is because the receiver does not know when the symbols will arrive, which can be due to a number of factors, including propagation delay between the Tx and Rx, particularly in a wireless communication environment where distances may become large. Another reason is that the transmitter and receiver clocks drift from their nominal values, forcing the receiver to continually adjust (or adapt) to maintain the appropriate sample time instance. By appropriate, it is desired that the sampling time instance match (or closely match) a maximum eye opening of the received signal, since this timing epoch corresponds to a maximum signal to noise ratio (SNR) value of the received signal.
One common method for continually adjusting to maintain the appropriate sample time instance is known as matched filter technique, which is illustrated in FIG. 2. In FIG. 2, a fixed oscillator 200 generates a constant frequency signal and supplies the same to an A/D converter 210. The A/D converter 210 converts the received signal into a digital signal using the frequency signal supplied from the fixed oscillator 200, and outputs the digitized signal to an interpolator 220. Meanwhile, a controller 230 receives a symbol timing error signal output from a timing error detector 250 via a loop filter 240. The controller 230 generates an interpolation coefficient according to the input symbol timing error signal and supplies the same to the interpolator 220. The interpolator 220 interpolates the digitized signal with the interpolation coefficient supplied from the controller 230, and outputs the interpolated result to a matching filter 260.
The A/D converter 210 samples the received signal at a sampling frequency supplied from the fixed oscillator 200 and converts the analog signal to the digital signal. The digitized signal is output via the interpolator 220 and the matching filter 260 and simultaneously input to the timing error detector 250. The symbol timing error signal which is detected in the timing error detector 250 and has noise removed in the loop filter 240 is then input to the controller 230. The controller 230 generates the interpolation coefficient according to the input signal. The interpolator 220 interpolates the digitized signal according to the interpolation coefficient supplied from the controller 230, and thereby removes the symbol timing error. Although this apparatus can accurately recover the symbol timing, it is very complicated to implement using hardware.
Other efforts at providing the needed symbol timing recovery include Choi, U.S. Pat. No. 5,872,818, which is incorporated herein by reference, in it""s entirety. Furthermore, in addition to Choi and the Matched Filter described above, many other techniques are available, such as Maximum Likelihood (ML), PLL-Based systems, DFT.
However, none of these techniques provide the best solution for modern digital communications devices. Moreover, the above techniques favor high resolution received signals. In this application, resolution refers to discrete time representations of a continuous signal. High resolution refers to a relatively large amount of bits in the ADC. For example, a number of bits (b), such as b greater than =6, are considered high resolution.
The present inventors have realized that modern digital communications systems fail to address the needs of applications of low resolution digital systems.
The present invention provides a robust method with good BER performance for low resolution signals. The present invention can be implemented without the complexities seen in the prior art, and can be modified for improved performance when high resolution signals are available.
Roughly described, the present invention provides Symbol Timing Recovery (STR) via a set of edge detections maintained in a histogram that are utilized to calculate the phase and timing of subsequently received symbols.
The present invention is embodied as a device, comprising, an ADC mechanism configured to sample a received signal at a predetermined over-sampling rate, a detector connected to said ADC mechanism and configured to detect a symbol identified by at least one of said samples during predetermined symbol times, and a symbol timing mechanism connected to said ADC mechanism and said detector and configured to read said samples and adjust a timing of the detection performed by said detector based on previously read samples so that the detected samples are at a most likely maximum eye opening of said samples during said predetermined symbol times.
The present invention includes a method of symbol timing, or recovery of symbol timing, comprising the steps of, sampling a received signal at a predetermined over-sampling rate, determining a timing for detection of a specific one or set of said samples based on historical data of samples previous samples, and detecting said specific one or predetermined number of samples based on the determined timing.
Both the device and method may be conveniently implemented on a general purpose computer, or networked computers, and the results may be displayed on an output device connected to any of the general purpose, networked computers, or transmitted to a remote device for output or display.